1. Field of the Invention
The present invention relates to a semiconductor memory device and, in particular, to a semiconductor memory device including a Write Data Through function which outputs input write data in a write operation.
2. Description of Related Art
FIG. 6 shows an example of a typical configuration of a semiconductor memory device. Digit lines and a portion surrounding an input and output circuits in the semiconductor memory device are mainly shown in FIG. 6. Referring to FIG. 6, PMOS transistors 301 and 302 having sources commonly connected to a power supply, gates commonly connected to a precharge control signal PC, and drains connected to digit lines DT and DB, respectively, are circuits that precharge the digit line pair DT/DB. A PMOS transistor 303 connected between the digit lines DT and DB and having a gate connected to the precharge control signal PC is a circuit that equalizes the digit line pair DT/DB. Each of digit line pairs DT [i]/DB [i] (where i is an integer in the range from 0 to c) is connected with multiple memory cells (not shown) and is selected by a word line (not shown) having a high electric potential. Y selectors 304, each of which is controlled to be turned on or off by a corresponding column select signal YSL [i] (where i is an integer in the range from 0 to c) among c+1 column select signals YSL [0:c] that are output from a column decoder, not shown, are connected to a common data line pair YDT/YDB. The Y selector (SEL) 304 may be implemented by an NMOS transistor that has a gate connected to a column select signal and is turned on when the column select signal is high, for example.
PMOS transistors 305 and 306 having sources commonly connected to a power supply, gates commonly connected to the precharge control signal PC, and drains connected to data lines YDT and YDB, respectively, are circuits that precharge the common data line pair YDT/YDB. A PMOS transistor 307 connected between the common data line pair YDT/YDB and having a gate connected to the precharge control signal PC is a circuit that equalizes the common data line pair YDT/YDB. The common data line pair YDT/YDB and a data line pair DLDT/DLDB on a sense amplifier 312 side are interconnected through a switch (transfer gate) 308.
PMOS transistors 309 and 310 having sources commonly connected to a power supply, gates commonly connected to the output of a NOR circuit 320, and drains connected to the data lines DLDT and DLDB, respectively, are circuits that precharge the data line pair DLDT/DLDB. A PMOS transistor 307 connected between the data line pair DLDT/DLDB and having a gate connected to the output of the NOR circuit 320 is a circuit that equalizes the data line pair DLDT/DLDB.
The data line pair DLDT/DLDB is coupled into first input terminals of NAND circuits 315 and 316, respectively. The output terminals of the NAND circuits 315 and 316 are connected to second input terminals of the NAND circuits 316 and 315, respectively. Output from the NAND circuit 315 is output to an output data terminal Q through an inverter (output buffer) 317. The NAND circuits 315 and 316 form an SR latch (SR flip-flop) which outputs a low-level signal when DLDT is high and outputs a high-level signal when DLDB is high. The SR latch (315, 316) and the inverter (output buffer) 317 constitute an output circuit.
The semiconductor memory device further includes a 2-input AND circuit 318 into which a write enable signal WE which goes high at a write and a one-shot pulse signal (referred to as an “internal clock signal”) ICL for RAM internal control are input, a 2-input NOR circuit 321 into which an output signal from the 2-input AND circuit 318 and a sense amplifier activation signal SESI are input, and an inverter 322 which inverts the output from the 2-input NOR circuit 321.
The output of the inverter 322 is connected to the gate of an NMOS transistor 313 out of two NMOS transistors 313 and 314 which are cascode-connected between the sense amplifier 312 and a GND as a signal SES for controlling activation of the sense amplifier 312. An output signal SESB from the 2-input NOR circuit 321 controls on and off of the switch 308.
An output signal from the 2-input NOR circuit 320 into which the internal clock signal ICL inverted by the inverter 319 and a write enable signal WE are input is input into the gates of PMOS transistors 309, 310, and 311 which precharge and equalize the data line pair DLDT/DLDB and also input into the gate of the NMOS transistor 313 out of the two NMOS transistors 313 and 314 cascode-connected between the sense amplifier 312 and the GND to control activation of the sense amplifier 312.
Write data input through an input data terminal is input into a D-type latch circuit 323. The D-type latch circuit 323 latches the write data in synchronization with the rising edge of the internal clock signal ICL. The write data latched in the D-type latch circuit 323 is input into a write buffer 324. The write buffer 324 outputs the input write data as a complementary signal. The output pair of the write buffer 324 is connected to a common data line pair YDT/YDB.
The following provides an overview of operation of the semiconductor memory device in FIG. 6.
Write access will be described first. At write access, the write enable signal WE is driven high. When the internal clock signal ICL is high, the output from the AND circuit 318 is driven high, the output signal SESB from the NOR circuit 321 goes low, the switch 308 is turned off, and the data line pair DLDT/DLDB is disconnected from the common data line pair YDT/YDB. The switch (transfer gate) 308 is formed by, but not limited to, two NMOS transistors (not shown) connected between DLDT and YDT and between DLDB and YDB, respectively, and having gates commonly connected to SESB. The output of the NOR circuit 320 into which a high-level WE is input is low and the NMOS transistor 314 whose gate is connected to the output of the NOR circuit 320 is turned off. Consequently, the sense amplifier 312 is deactivated. The PMOS transistors 309 to 311 whose gates are connected to the output of the NOR circuit 320 are turned on to precharge and equalize the data line pair DLDT/DLDB.
In response to transition of ICL from low to high, the D-type latch circuit 323 latches write data input into the input data terminal D. The write buffer 324 which receives the write data which is single-ended output from the D-type latch circuit 323 differentially outputs the write data to the common data line pair YDT/YDB. The write data differentially output onto the common data line pair YDT/YDB is transmitted to the digit line pair DT/DB of a selected column via a Y selector 304 that is set on by a column select signal and the write data is written in a memory cell connected to a selected word line. Then, ICL drops from high to low and the precharge control signal PC goes low to precharge the digit line pair YDT/YDB.
Read access will be described next. When read access is made, the write enable signal WE is driven low and the output from the AND circuit 318 is driven low. The output signal SESB from the NOR circuit 321 goes high when the sense amplifier activation control signal SESI is low and goes low when SESI is high. That is, when SESI is low, SESB goes high and the switch 308 is turned on to connect YDT with DLDT and connect YDB with DLDB. When SESI is high, SESB goes low and the switch 308 is turned off to disconnect YDT from DLDT and YDB from DLDB. Output SES from the inverter 322 goes high to turn on the NMOS transistor 313. The output from the NOR circuit 320 into which the low-level write enable signal WE is input goes high and turns on the NMOS transistor 314 when ICL is high. When ICL drops from high to low, the output from the NOR circuit 320 goes low to turn off the NMOS transistor 314, turn on the PMOS transistors 309, 310, and 311, and precharge and equalize the data line pair DLDT/DLDB.
That is, when SESI is low in a read cycle, the output SESB from the NOR circuit 321 goes high and the switch 308 turns on. When SESI is high, the output SESB of the NOR circuit 321 goes low, the switch 308 is turned off, and the signal SES applied to the gate of the NMOS transistor 313 is driven high. When ICL is high in this state, the output from the NOR circuit 320 goes high and a high-level signal is applied to both of the gates of the NMOS transistors 313 and 314. Thus, both of the NMOS transistors 313 and 314 are turned on to activate the sense amplifier 312.
A signal (read data) amplified by the sense amplifier 312 and output to the data line pair DLDT/DLDB is latched in the SR latch (315, 316) and then output to the output data terminal through the output buffer 317. Then, when ICL falls low, the output from the NOR circuit 320 goes low and the PMOS transistors 309, 310, and 311 precharge and equalize the data line pair DLDT/DLDB.
Japanese Patent Laid-Open No. 2004-199814 describes a semiconductor memory device including the Write Data Through function or mode which receives write data input through an input data terminal D and directly outputs the write data from the output data terminal Q in a data write operation. The Document discloses a configuration that implements a write through function (Write Data Through function) with a short read time.
Based on the semiconductor memory device circuit shown in FIG. 6, a semiconductor memory device will be considered below that includes the Write Data Through function. The semiconductor memory device including the Write Data Through function has a configuration as shown in FIG. 5, for example. It should be noted that FIG. 5, which has been drawn by the inventor, shows an example of write through control to be compared with the present invention and does not show the conventional art.
Referring to FIG. 5, an output pair of a write buffer 220 which receives write data latched in and output from a D-type latch circuit 219 is connected to a common data line pair YDT/YDB.
In a write operation, an output from the D-type latch circuit 219 is provided to the data line pair YDT/YDB through the write buffer 220 at the rising edge of an internal clock signal ICL and transmitted to a digit line pair DT/DB of a selected column through a Y switch 204 turned on by a column select signal, and is written in a memory cell of a selected word line. When a sense amplifier activation control signal SESI is low, an output from a NAND circuit 218 goes high and a switch (transfer gate) 208, which controls connection between YDT/YDB and DLDT/DLDB to turn on or off, is turned on to bring YDT/YDB, DLDT and DLDB into conduction. The switch 208 is formed by, but not limited to, two NMOS transistors connected between DLDT and YDT and between DLDB and YDB, respectively, and having gates commonly connected to SESB.
When both SESI and ICL are high, the output signal SESB from the NAND circuit 218 goes low, the switch 208 is turned off, and YDT/YDB and DLDT/DLDB are disconnected. On the other hand, when the output SES from an inverter 217 goes high, an NMOS transistor 213 is turned on, a current is supplied to a sense amplifier 212 to activate the sense amplifier 212, and the sense amplifier 212 outputs the result of sense and amplification to DLDT/DLDB. An SR latch circuit (NAND circuits 214 and 215 having cross-coupled inputs and outputs) which receives a signal from DLDT/DLDB outputs a latched output to an inverter (inverting buffer) 216, and the inverter 216 outputs the inverted signal to an output data terminal Q. That is, the write data from the D-type latch circuit 219 is output from the output data terminal Q through a path indicated by the return arrow in FIG. 5.
When ICL is low or SESI is low, the output from the NAND circuit 218 is driven high, the switch 208 is turned on, and YDT/YDB are connected with DLDT/DLDB. When both SESI and ICL are high in read operation, the output from the NAND circuit 218 goes low, the switch 208 is turned off, and YDT/YDB are disconnected from DLDT/DLDB. The output from the inverter 217 is driven high, the NMOS transistor 213 is turned on, the sense amplifier 212 is activated, and the sense amplifier 212 senses and amplifies the signal from DLDT/DLDB. The SR latch circuit which receives the signal from DLDT/DLDB outputs a latched output to the inverter 216 and the inverter 216 outputs the inverted signal to the output data terminal Q.
FIG. 7 is a timing chart when write and read operations of the semiconductor memory device (RAM) shown in FIG. 5 is performed. In a read operation (Read Cycle), access time is slow because the access passes through a memory cell and is kept waiting until a potential difference greater than or equal to a limit of sense and amplification operation is ensured. tOHR is the time period between the start of the read cycle (the rising edge of an external clock CLK) and the output of read data to the output terminal Q.
On the other hand, in a Write Data Through operation in write operation, access time is fast because input write data is passed directly through to the output data terminal Q without passing through a memory cell. Time tOHW (data hold time) is equal to the time period between the start of a write cycle (rising edge of the external clock CLK) and the output of write data to the output data terminal Q without passing through the memory cell.
That is, in a Write Data Through operation, input write data is transmitted to the output data terminal Q through the write buffer 220 which receives the write data output from the D-type latch circuit 219 in response to the rising edge of an internal clock signal ICL, and through YDT/YDB and DLDT/DLDB. Therefore, the data hold time tOHW is short. On the other hand, in a read operation, the sense amplifier 212 is activated and then a change occurs at the output data terminal Q after the rising edge of SESI. Therefore, data hold time tOHR is longer than that in a write operation.
Since a write operation in which the access time is relatively fast is performed after a read operation in which access time is relatively slow in the configuration shown in FIG. 5, the valid range of input data on a chip (CPU or controller) side is extremely reduced when intermittent read and write operations or alternating read and write operations are performed. That is, the time period during which write data is output and held on a data bus connecting to the semiconductor memory device (RAM) on the chip (CPU or controller) side is extremely short in a Write Data Through operation. Consequently, timing margin of chip design is extremely small.
Furthermore, in order to meet specifications of different semiconductor memory devices (RAMs), hardware of the RAMs must be individually designed. RAMs that meet customers' specifications must be individually designed. Accordingly, the load of designing RAMs increases.